When you first learn about digital logic, it probably seems like it is easy. You learn about AND and OR gates and figure that’s not very hard. However, going from a few basic gates to something like a ...

When designing a chip, a designer needs to consider many tradeoffs before developing the logic. For example, if a chip is being developed for mobile applications, power becomes a very important factor ...

We’ve seen a few 1-D pong games recently, and they’ve all be controlled using microcontrollers. Inspired by some of these hacks, [mischka] built the monoPong using a handful of logic chips. The ...

Designing high-speed digital systems on FPGA platforms has always been challenging. The large amounts of routing required by SRAM-based FPGAs often limits system performance to well below that ...

As technologies shrink, design architectures evolve, and higher speeds are required, more complex issues and strategies have surfaced relating to CTS. A surefire way to ensure a design’s success lies ...

Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...

The quantum logic clock--perhaps best known for showing you age faster if you stand on a stool--has climbed back to the leading performance echelons of the world's experimental atomic clocks.