If you have been following my month of power over on the EE Times EDA Designline, you will know that I have been featuring books that tackle the subject of power integrity. It should tell you ...

At 10nm and beyond, the breakdown of some historic trends tied to Moore’s Law is making it harder to fully harvest the benefits of scaling semiconductor technologies. Underlying the power, performance ...

If you're looking to distinguish yourself in an up-and-coming area of engineering, power integrity (PI) could be for you. The impressive number of DesignCon 2016 sessions (and a PI boot camp) were ...

As designs increase in complexity to cater to the insatiable need for more compute power — which is being driven by different AI applications ranging from data centers to self-driving cars—designers ...

A decade ago, the call of the times was for solutions to address the “Power Wall†, at least at leading microprocessor institutions. Conferences discussed looming challenges with supply currents ...

Tightly integrated with key Cadence tools throughout the design flow, including Cadence Tempus Timing Signoff Solution, for the fastest design closure in the industry "As a global leader in embedded ...

For many years, power systems could be easily boiled down to a discussion of volts and amps. But for the past decade, the move to higher operating frequencies has brought another wrinkle to the power ...

IC designers know the litany backwards and forwards: Area, power, and speed are the primary tradeoffs when it comes to optimizing your designs. You can usually have two out of the three, but a design ...