EDN

Verification reuse ensures predictable design

Your system-on-chip is made up of well-designed modules. The crack design team has covered every base, verifying each piece. Now you're integrating the modules into subassemblies and into a complete ...
Design-Reuse

Cadence Enhances Low-Power Solution Enabling More Predictable Power-Efficient Design

New Capabilities for Macro Modeling, IP Integration and Metric-Driven Verification are Built Upon Updated Standard SAN JOSE, Calif. -- Mar 16, 2009 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the ...
autoevolution

Audi to Put an End to Its Predictable Design Approach, Go for (Some) Diversity

There aren't that many complaints you can have about the Audi range, but that's because it all feels like one design scaled to fit into every different segment. Despite constant negative feedback from ...
Nasdaq

Synopsys and Samsung Foundry Announce Reference Flow for Predictable Execution of ASIL D-Compliant SoC Design for Automotive Applications

Samsung Foundry and Synopsys' optimized flow achieves predictable execution of in-system test, implementation, verification, timing and physical signoff for ASIL D-compliant SoC design Includes ...
EDN

Cadence enhances low-power solution to make power-efficient designs more predictable

Winchester, UK – Cadence Design Systems, Inc., has enhanced the Cadence Low-Power Solution to include support for new on-chip power management schemes enabled by the recently ratified Si2 Common Power ...