EDN

Using SystemVerilog for functional verification

The need to improve functional verification productivity and quality continues to grow. The 2004/2002 IC/ASIC Functional Verification Study, by Collett International Research, shows that logic or ...
Semiconductor Engineering

Simplifying SystemVerilog Functional Coverage

Let’s say you have a block you need to verify. How do you know that the stimulus you are about to use is exhaustive enough and that you have covered the necessary scenarios/situations to prove it is ...
EDN

SystemVerilog assertions unify design and verification

The SystemVerilog standard is the result of an industry-wide effort to extend the Verilog language in a consistent way to include enhanced modeling and verification features. By adding verification ...
Electronic Design

SystemVerilog Gains A Foothold In Verification

Indeed, designers have embraced SystemVerilog—it's by far the fastest growing design/verification language in the world today (Fig. 1). "The ability to do assertions is significantly improved in ...
Design-Reuse

A Step By Step Methodical Approach for Efficient Mixed-Language IP Integration

--The wide variety of design languages available today poses a significant barrier to IP reuse. SystemC, SystemVerilog, and conventional HDL languages have unique strengths which make them more ...
Semiconductor Engineering

Making Declarative Modeling Modular: Portable Stimulus Introduces Dynamic Constraints

Naturally, Accellera’s Portable Stimulus Standard (PSS) supports the powerful capabilities of advanced verification techniques that are well-known in the industry today, including object-oriented ...
Electronic Design

What’s the Difference Between VHDL, Verilog, and SystemVerilog?

Designers of electronic hardware describe the behavior and structure of system and circuit designs using hardware description languages (HDLs)—specialized programming languages commonly known as VHDL, ...