GitHub

SystemVerilog Functional Coverage for RISC-V ISA

This project is a work in progress (started in early 2022) to provide the RISC-V Verification ecosystem and users an immediate solution to SystemVerilog Functional Coverage for the RISC-V ISA. The ...
IEEE

Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore

Abstract: Existing tiled manycore architectures propose to convert abundant silicon resources into general-purpose parallel processors with unmatched computational density and programmability. However ...
GitHub

Working draft of the proposed RISC-V V vector extension.

Version 1.0 has been frozen and at this time is undergoing public review. Version 1.0 is considered stable enough to begin developing toolchains, functional simulators, and implementations, including ...
IEEE

Designing and Implementation of 32-bit 5 stage Pipelined MIPS based RISC Processor Capable of Resolving Data Hazards

Abstract: The main objective is to design and implement a 5-stage pipelined 32-bit High performance RISC Processor with MIPS architecture which is also capable in detecting and resolving Data Hazards.