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Definition of cache coherency
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SOLVED: Using the MSI state transition of a block for cache coherency of two cores that are sharing memory but have their own L1 cache, fill in the table below:SNOOP RD, WR ON BUSLOCAL READLOCAL READ PUT RD ON BUSINVALID V=0SHARED V=1 D=0SNOOP RD ON BUSSNOOP WR ON BUSLOCAL SNOOP WRITEWR ON BUSSNOOP RD ON BUSWRITEWRITE BUS BACKBACKLOCAL MODIFIED WRITEPUT V=0INVALIDATION D=1 ON BUSLOCAL READLOCAL WRITEC1C2CState of C1 L1State of C2 L1Read XRead XWrite XWrite X
SOLVED: Using the MSI state transition of a block for cache coh…
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